As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software resources that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Double-Data Rate-4 (DDR4) memory is a high speed memory technology that supports data transfer rates of between 2133 and 3200 million transfers per second (MT/s). Previous memory technologies included sufficient margins to permit a specific bit-error rate (BER) of zero (0). However, noise and jitter margins for DDR4 have shrunk to the point that a specification of a zero BER is impractical. As such, the specification for DDR4 provides a BER of 10−16 errors per bit, which corresponds to the average statistical transmission of 1016 bits or more without error. Future memory technologies will likely continue to specify low BER.
Validation of memory channels in an information handling system has typically included time-domain design simulation, such as using a Spice simulator, in conjunction with on-system testing of the memory channels to ensure that the information handling system meets the desired performance level. However, the large number of cycles necessary to validate to the DDR4 BER makes full simulation impractical, and lengthens the duration of on-system testing.
The use of the same reference symbols in different drawings indicates similar or identical items.